• Operating Conditions

• 3.0V to 3.6V

• -40ºC to +125ºC, DC to 100 MHz

• -40ºC to +150ºC, DC to 70 MHz

• dsPIC33CK DSC Core

• Up to 256 KBytes of Program Flash with ECC and Live Update (dual-partition Flash)

• Up to 24 KBytes of Data SRAM with Memory Built in Self-Test (MBIST)

• Modified Harvard architecture with 16-bit data and 24-bit instructions

• Code efficient (C and Assembly) CPU architecture designed for real-time applications

• 16x 16-bit working registers

• 4 sets of interrupt context saving registers, including ACC and CPU status for fast interrupt handling

• Single-cycle, mixed-sign 32-bit MUL

• Fast 6-cycle hardware 32/16 and 16/16 DIV

• Dual 40-bit fixed point Accumulators (ACC) for DSP operations

• Single-cycle MAC/MPY with dual data fetch and result write-back

• Zero overhead looping support

• High-Speed PWM Module

• 8 independent PWM pairs (16 total outputs) with up to 250ps resolution

• Dead-time insertion for rising and falling edges and dead-time compensation support

• Clock chopping for high-frequency operation

• Fault and current limit inputs

• Flexible trigger configuration for ADC triggering

• Advanced Analog Features

• 3 12-bit 3.5 MSPS ADC Modules each with 2 dedicated SARs and 1 shared SAR cores (3 S&Hs)

• 12, 16, 19, 20 or 24 ADC input channels (depending on package)

• 4 digital comparators for reducing CPU overhead

• 4 oversampling filers up to 256x for increased resolution (up to 16-bits)

• 3 analog comparators (15ns) with dedicated 12-bit DACs with hardware slope compensation

• Up to 3 op amps with internal connection to ADC Module

• Functional Safety Support (ISO 26262 and IEC 61508)

• ISO 26262 and IEC 61508 Functional Safety Ready

• ASIL B automotive safety applications – ISO 26262

• SIL 2 industrial safety applications – IEC 61508

• ISO 26262 and IEC 61508 Functional Safety Packages

• Embedded Security

• CodeGuard security together with Flash OTP by ICSP Write Inhibit enables implementing Immutable Secure Boot

• Flash OTP by ICSP Write Inhibit to configure entire Flash as OTP

• Option to disable entry to the debug mode

• User OTP

• Enables implementing robust security use cases together with CryptoAuthentication and CryptoAutomotive devices such as:

• Secure Boot

• Secure Firmware Upgrade

• Secure Communication

• Node Authentication and more

• Timer/Counters/Output Compare/Input Capture

• 10 16-bit timer/counters (up to 4 32-bit)

• 14 PWM or Output Compare (OC) outputs

• 9 Input Captures (IC) pins or internal connections from the CLC or Comparator Modules

• Peripheral Trigger Generator (PTG) for scheduling complex sequences

• 2 Quadrature Encoder Interface (QEI) Modules for optical encoder support

• Communication Interfaces

• 3 UARTs (15 Mbps) with automated protocol handling for LIN/J2602, DMX and IrDA®

• 3 4-wire SPI/I2S up to 40 MHz with dedicated pins

• 3 I2C Modules (up to 1 Mbps) with SMBus support

• CAN Flexible Data Rate (CAN-FD) Module ("50x devices only)

• 2 Single-Edge Nibble Transmission (SENT) Modules for sensor interfacing

• 4 DMA channels supporting UART, SPI, ADC, CAN-FD, IC, OC and Timer data transfers

• Special Features

• 4 Configurable Logic Cell (CLC) Modules with user defined logic gate circuits

• Programmable Pin Select (PPS) for peripheral pin function mapping

• Parallel Master Port (PMP) for external data expansion

• On-chip temperature sensor with direct ADC Module connection

• Clock and Power Management

• On-chip 8 MHz Fast RC (FRC) and 32 kHz Low-Power RC (LPRC) oscillators

• Programmable PLLs with external oscillator clock sources and Reference Clock Output (REFO)

• Fail-Safe Clock Monitor (FSCM) with 8 MHz Back-up Fast RC (BFRC) oscillator

• Low-Power management modes - Sleep, Idle and Doze

• Integrated Power-on Reset (POR) and Brown-Out Reset (BOR)

• Debugger Development Support

• In-Circuit and in application programming and debug support (ICSP)

• On-chip debug trace buffer and run-time watch with 3 complex and 5 simple breakpoints

• IEEE 1149.2 (JTAG) boundary scan support

• Functional Safety hardware features

• Dead-Man Timer (DMT) safety feature clocked by instruction fetches

• Windowed Watch Dog Timer (WDT)

• CodeGuard™ security for program FLASH

• Programmable Cyclic Redundancy Check (CRC)

• FLASH ECC Fault Injection testing feature

• Flash OTP by ICSP™ write inhibit

• RAM Memory Built in Self-Test (MBIST)

• Clock Monitor with multiple redundant clock sources

• Analog peripherals redundancies

• Write protection

• Hardware traps

• SFR locks

• Shadow working registers

• PWM Fault Management

• cap-less on-chip LDO

• I/O Port read-back

• Class B Safety Library, IEC 60730

• AUTOSAR-Ready DSC supporting:

• AUTOSAR (4.3.x)

• ASIL B- and ASPICE-compliant MCAL drivers

• ISO 26262 Functional Safety and Automotive Security

Parametrics