MX25L12835FM2I-10G
MX25L12835F为128Mb位串行Flash内存,内部配置为16,777,216 * 8。当它处于2或4个I/O模式时,结构变成67,108,864位x 2或33,554,432位x 4。MX25L12835F具有串行外设接口和软件协议,允许在单一I/O模式下在简单的3线总线上操作。三个总线信号分别是时钟输入(SCLK)、串行数据输入(SI)和串行数据输出(SO)。对设备的串行访问通过c#input启用。当它处于两个I/O读取模式时,SI引脚和SO引脚变成SIO0引脚和SIO1引脚用于地址/虚位输入和数据输出。当它处于四个I/O读模式时,SI引脚、SO引脚、WP#和RESET#引脚变成SIO0引脚、SIO1引脚、SIO2引脚和SIO3引脚,用于地址/虚位输入和数据输出。MX25L12835F MXSMIO(串行多I/O)在整个芯片上提供顺序读操作。在发出program/erase命令后,将自动执行program/erase算法,该算法对指定的页或扇区/块位置进行编程/erase和验证。程序命令以字节、页(256字节)或字为基础执行,而擦除命令则以扇区(4k字节)、块(32k字节)或块(64k字节)或整个芯片为基础执行。为了给用户提供方便的界面,包括一个状态寄存器来指示芯片的状态。状态读取命令可以通过WIP位来检测程序的完成状态或擦除操作。先进的安全功能增强了防护和安全功能,详情请参见安全功能部分。当设备未运行且CS#值高时,设备进入待机模式。
MX25L12835F采用了宏宏的专有存储单元,即使经过100,000个程序和擦除周期,也能可靠地存储内存内容。
特性
•支持串行外设接口-模式0和模式3
•单电源操作-2.7至3.6伏用于读取、擦除和程序操
•128Mb: 134,217,728 × 1位结构或671,08,864 × 2位(2个I/O模式)结构或33,554,432 × 4位(4个I/O模式)结构
•协议支持
-单I/O,双I/O和四I/O
•闭锁保护100mA从-1V到Vcc +1V
•快速读取SPI模式
-支持所有协议最高133MHz的时钟频率
-支持快速读取,2READ,恐惧,4READ, QREAD指令。
—可配置虚拟循环号,快速读取操作
•四外设接口(QPI)可用
•每个4K字节的相等扇区,或每个32K字节的相等块或每个64K字节的相等块
—任何Block都可以被单独擦除
•编程:
- 256字节的页面缓冲区
-四输入/输出页程序(4PP),提高程序性能
•典型的100,000个擦除/程序周期
•数据保留20年
MX25L12835FM2I-10G
MX25L12835F is 128Mb bits serial Flash memory, which is configured as 16,777,216 x 8 internally. When it is in two or four I/O mode, the structure becomes 67,108,864 bits x 2 or 33,554,432 bits x 4. MX25L12835F feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input.When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# and RESET# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.The MX25L12835F MXSMIO (Serial Multi I/O) provides sequential read operation on whole chip.After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis for erase command is executed on sector (4K-byte), block (32K-byte), or block (64K-byte), or whole chip basis.To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit.Advanced security features enhance the protection and security functions, please see security features section for more details.When the device is not in operation and CS# is high, it is put in standby mode.The MX25L12835F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles.
FEATURES
GENERAL
• Supports Serial Peripheral Interface -- Mode 0 and Mode 3• Single Power Supply Operation- 2.7 to 3.6 volt for read, erase, and program operations• 128Mb: 134,217,728 x 1 bit structure or 67,108,864 x 2 bits (two I/O mode) structure or 33,554,432 x 4 bits (four I/O mode) structure• Protocol Support- Single I/O, Dual I/O and Quad I/O• Latch-up protected to 100mA from -1V to Vcc +1V• Fast read for SPI mode- Support clock frequency up to 133MHz for all protocols- Support Fast Read, 2READ, DREAD, 4READ, QREAD instructions.- Configurable dummy cycle number for fast read operation• Quad Peripheral Interface (QPI) available• Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each- Any Block can be erased individually• Programming :- 256byte page buffer- Quad Input/Output page program(4PP) to enhance program performance• Typical 100,000 erase/program cycles• 20 years data retention