IS42S32800J-7TLI-TR

ISSI的256Mb同步DRAM采用流水线架构实现高速数据传输。所有输入输出信号都是指时钟输入的上升沿。256Mb的SDRAM被组织成2Meg x 32 bit x 4 bank

Descroption

The 256Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V Vdd and 3.3V Vddq memory systems containing 268,435,456 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 67,108,864-bit bank is organized as 8,192 rows by 512 columns by 16 bits or 8,192 rows by 1,024 columns by 8 bits. The 256MbSDRAM includes anAUTOREFRESH MODE, and a power-saving, power-down mode. All signals are  registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The 256Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address  generation, the ability to interleave between internal banks  to hide precharge time and the capability to randomly  change column addresses on each clock cycle during  burst access.

A self-timed row precharge initiated at the end of the burst  sequenceisavailablewiththeAUTOPRECHARGEfunction enabled. Precharge one bank while accessing one of the  other three banks will hide the precharge cycles and provide  seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting  at a selected location and continuing for a programmed  number of locations in a programmed sequence. The registration of an ACTIVE command begins accesses, followed by a READ or WRITE command. The ACTIVE command in conjunction with address bits registered are  used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The READ or WRITE commands in conjunction with address bits registered are used to select the starting column location  for the burst access. Programmable READ or WRITE burst lengths consist of 1, 2, 4 and 8 locations or full page, with a burst terminate option.

简述

256Mb SDRAM是一种高速CMOS动态随机存取存储器，设计用于3.3V Vdd和3.3V Vddq存储系统，包含268,435,456位。内部配置为具有同步接口的四组DRAM。每个67,108,864位的银行组织为，组织为8,192行乘512列乘16位或8,192行乘1,024列乘8位。256MbSDRAM包括autorefresh MODE和省电、下电模式。所有信号都注册在时钟信号的正边，CLK。所有输入和输出LVTTL兼容。256Mb SDRAM具有以高数据速率同步突发数据的能力，具有自动生成列地址的能力，能够在内部银行之间交错以隐藏预充电时间，并且能够在突发访问期间随机更改每个时钟周期的列地址。

在burst序列结束时启动的自定时行预充可以使用autoprecharge_enabled功能。在访问其他三家银行之一的同时对一家银行进行预充，将隐藏预充周期，并提供无缝，高速，随机访问的操作。SDRAM读写访问是面向突发的，从一个选定的位置开始，并在一个已编程的序列中为已编程的位置数继续。注册ACTIVE命令开始访问，然后是READ或WRITE命令。ACTIVE命令与注册的地址位一起用于选择要访问的银行和行(BA0, BA1选择银行;A0-A12选择行)。READ或WRITE命令与注册的地址位一起用于选择突发访问的起始列位置。可编程读或写突发长度包括1,2,4和8个位置或整页，具有突发终止选项。

IS42S32800J-7TLI-TR

ISSI的256Mb同步DRAM采用流水线架构实现高速数据传输。所有输入输出信号都是指时钟输入的上升沿。256Mb的SDRAM被组织成2Meg x 32 bit x 4 bank

Descroption

The 256Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V Vdd and 3.3V Vddq memory systems containing 268,435,456 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 67,108,864-bit bank is organized as 8,192 rows by 512 columns by 16 bits or 8,192 rows by 1,024 columns by 8 bits. The 256MbSDRAM includes anAUTOREFRESH MODE, and a power-saving, power-down mode. All signals are  registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The 256Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address  generation, the ability to interleave between internal banks  to hide precharge time and the capability to randomly  change column addresses on each clock cycle during  burst access.

A self-timed row precharge initiated at the end of the burst  sequenceisavailablewiththeAUTOPRECHARGEfunction enabled. Precharge one bank while accessing one of the  other three banks will hide the precharge cycles and provide  seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting  at a selected location and continuing for a programmed  number of locations in a programmed sequence. The registration of an ACTIVE command begins accesses, followed by a READ or WRITE command. The ACTIVE command in conjunction with address bits registered are  used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The READ or WRITE commands in conjunction with address bits registered are used to select the starting column location  for the burst access. Programmable READ or WRITE burst lengths consist of 1, 2, 4 and 8 locations or full page, with a burst terminate option.

简述

256Mb SDRAM是一种高速CMOS动态随机存取存储器，设计用于3.3V Vdd和3.3V Vddq存储系统，包含268,435,456位。内部配置为具有同步接口的四组DRAM。每个67,108,864位的银行组织为，组织为8,192行乘512列乘16位或8,192行乘1,024列乘8位。256MbSDRAM包括autorefresh MODE和省电、下电模式。所有信号都注册在时钟信号的正边，CLK。所有输入和输出LVTTL兼容。256Mb SDRAM具有以高数据速率同步突发数据的能力，具有自动生成列地址的能力，能够在内部银行之间交错以隐藏预充电时间，并且能够在突发访问期间随机更改每个时钟周期的列地址。

在burst序列结束时启动的自定时行预充可以使用autoprecharge_enabled功能。在访问其他三家银行之一的同时对一家银行进行预充，将隐藏预充周期，并提供无缝，高速，随机访问的操作。SDRAM读写访问是面向突发的，从一个选定的位置开始，并在一个已编程的序列中为已编程的位置数继续。注册ACTIVE命令开始访问，然后是READ或WRITE命令。ACTIVE命令与注册的地址位一起用于选择要访问的银行和行(BA0, BA1选择银行;A0-A12选择行)。READ或WRITE命令与注册的地址位一起用于选择突发访问的起始列位置。可编程读或写突发长度包括1,2,4和8个位置或整页，具有突发终止选项。