IS61WV102416BLL-10TLI简介

DESCRIPTION TheISSIIS61WV102416ALL/BLLandIS64WV102416BLL are high-speed, 16M-bit static RAMs organized as 1024K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The device is packaged in the JEDEC standard 48-pin TSOP Type I and 48-pin Mini BGA (9mm x 11mm).

IS61WV102416BLL-10TLI参数

FEATURES

• High-speed access times:8, 10 20 ns

• High-performance, low-power CMOS process

• Multiple center power and ground pins for greater noise immunity

• Easy memory expansion with CE and OE options

• CE power-down

• Fully static operation: no clock or refresh

IS61WV102416BLL-10TLI电压

required

• TTL compatible inputs and outputs

• Single power supply

Vdd 1.65V to 2.2V (IS61WV102416ALL)

speed = 20ns for Vdd 1.65V to 2.2V

Vdd 2.4V to 3.6V (IS61/64WV102416BLL)

speed = 10ns for Vdd 2.4V to 3.6V

speed = 8ns for Vdd 3.3V + 5%

IS61WV102416BLL-10TLI封装

Packages available:

         – 48-ball miniBGA (9mm x 11mm)

– 48-pin TSOP (Type I)

• Industrial and Automotive Temperature Support

• Lead-free available

• Data control for upper and lower bytes

IS61WV102416BLL-10TLI简介

DESCRIPTION TheISSIIS61WV102416ALL/BLLandIS64WV102416BLL are high-speed, 16M-bit static RAMs organized as 1024K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The device is packaged in the JEDEC standard 48-pin TSOP Type I and 48-pin Mini BGA (9mm x 11mm).

IS61WV102416BLL-10TLI参数

FEATURES

• High-speed access times:8, 10, 20 ns

• High-performance, low-power CMOS process

• Multiple center power and ground pins for greater noise immunity

• Easy memory expansion with CE and OE options

• CE power-down

• Fully static operation: no clock or refresh

IS61WV102416BLL-10TLI电压

required

• TTL compatible inputs and outputs

• Single power supply

 Vdd 1.65V to 2.2V (IS61WV102416ALL)

 speed = 20ns for Vdd 1.65V to 2.2V

 Vdd 2.4V to 3.6V (IS61/64WV102416BLL)

 speed = 10ns for Vdd 2.4V to 3.6V

 speed = 8ns for Vdd 3.3V + 5%

IS61WV102416BLL-10TLI封装

Packages available:

         – 48-ball miniBGA (9mm x 11mm)

 – 48-pin TSOP (Type I)

• Industrial and Automotive Temperature Support

• Lead-free available

• Data control for upper and lower bytes