The 25 series Serial Flash family features a four-wire, SPIcompatible interface that allows for a low pin-count package which occupies less board space and ultimately lowers total system costs. The SST25VF040B devices are enhanced with improved operating frequency for lower power consumption. SST25VF040B SPI serial flash memories are manufactured with SST proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches.

Please consider this device SST25PF040C

Additional Features

• Serial Interface Architecture

• SPI Compatible: Mode 0 and Mode 3

• Supports 50 MHz SPI clock (80MHz no longer available see EOL NOTIFICATION)

• Low Power Consumption:

• Active Read Current: 10 mA (typical)

• Program & Erase Current: 30mA (max)

• Standby Current: 5 µA (typical)

• Flexible Erase Capability

• Uniform 4 KByte sectors

• Uniform 32 KByte and 64 KByte overlay blocks

• Fast Erase and Byte-Program:

• Chip-Erase Time: 35 ms (typical)

• Sector-/Block-Erase Time: 18 ms (typical)

• Byte-Program Time: 7 µs (typical)

• Auto Address Increment (AAI) Programming

• Decrease total chip programming time overByte-Program operations

• Packages Available

• 8-lead SOIJ (200 mils)

• 8-lead SOIC (150 mils)

• 8-contact WSON (6mm x 5mm)

• Chip Scale Package

• All devices are RoHS compliant

The 25 series Serial Flash family features a four-wire, SPIcompatible interface that allows for a low pin-count package which occupies less board space and ultimately lowers total system costs. The SST25VF040B devices are enhanced with improved operating frequency for lower power consumption. SST25VF040B SPI serial flash memories are manufactured with SST proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches.

Please consider this device SST25PF040C

• Serial Interface Architecture

• SPI Compatible: Mode 0 and Mode 3

• Supports 50 MHz SPI clock (80MHz no longer available see EOL NOTIFICATION)

• Low Power Consumption:

• Active Read Current: 10 mA (typical)

• Program & Erase Current: 30mA (max)

• Standby Current: 5 µA (typical)

• Flexible Erase Capability

• Uniform 4 KByte sectors

• Uniform 32 KByte and 64 KByte overlay blocks

• Fast Erase and Byte-Program:

• Chip-Erase Time: 35 ms (typical)

• Sector-/Block-Erase Time: 18 ms (typical)

• Byte-Program Time: 7 µs (typical)

• Auto Address Increment (AAI) Programming

• Decrease total chip programming time overByte-Program operations

• Packages Available

• 8-lead SOIJ (200 mils)

• 8-lead SOIC (150 mils)

• 8-contact WSON (6mm x 5mm)

• Chip Scale Package

• All devices are RoHS compliant