W25Q128BVSIG简介

The W25Q128JV (128M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption as low as 1µA for power-down. All devices are offered in space-saving packages. The W25Q128JV array is organized into 65,536 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q128JV has 4,096 erasable sectors and 256 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See Figure 2.) The W25Q128JV supports the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 and I/O3. SPI clock frequencies of W25Q128JV of up to 133MHz are supported allowing equivalent clock rates of 266MHz (133MHz x 2) for Dual I/O and 532MHz (133MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. Additionally, the device supports JEDEC standard manufacturer and device ID and SFDP, and a 64-bit Unique Serial Number and three 256-bytes Security Registers.

W25Q128BVSIG参数

FEATURES

 New Family of SpiFlash Memories

– W25Q128JV: 128M-bit / 16M-byte

– Standard SPI: CLK, /CS, DI, DO

– Dual SPI: CLK, /CS, IO0, IO1

– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3

– Software & Hardware Reset(1)Highest Performance Serial Flash

– 133MHz Single, Dual/Quad SPI clocks

– 266/532MHz equivalent Dual/Quad SPI

– 66MB/S continuous data transfer rate

– Min. 100K Program-Erase cycles per sector

– More than 20-year data retentionEfficient “Continuous Read”

– Continuous Read with 8/16/32/64-Byte Wrap

– As few as 8 clocks to address memory

– Allows true XIP (execute in place) operation Low Power, Wide Temperature Range

– Single 2.7 to 3.6V supply

– <1µA Power-down (typ.)

– -40°C to +85°C operating range

– -40°C to +105°C operating range

 Flexible Architecture with 4KB sectors

– Uniform Sector/Block Erase (4K/32K/64K-Byte)

– Program 1 to 256 byte per programmable page

– Erase/Program Suspend & Resume Advanced Security Features

– Software and Hardware Write-Protect

– Power Supply Lock-Down

– Special OTP protection

– Top/Bottom, Complement array protection

– Individual Block/Sector array protection

– 64-Bit Unique ID for each device

– Discoverable Parameters (SFDP) Register

– 3X256-Bytes Security Registers with OTP locks

– Volatile & Non-volatile Status Register Bits Space Efficient Packaging

– 8-pin SOIC 208-mil

– 16-pin SOIC 300-mil (additional /RESET pin)

– 8-pad WSON 6x5-mm / 8x6-mm

– 24-ball TFBGA 8x6-mm (6x4/5x5 ball array)

– 24-ball WLCSP

– Contact Winbond for KGD and other options

Note: 1. Hardware /RESET pin is only available on

TFBGA or SOIC16 packages

W25Q128JVSIQ封装设计图

W25Q128JVSIQ型号解析

W25Q128JVSIQ简介

The W25Q128JV (128M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption as low as 1µA for power-down. All devices are offered in space-saving packages. The W25Q128JV array is organized into 65,536 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q128JV has 4,096 erasable sectors and 256 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See Figure 2.) The W25Q128JV supports the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 and I/O3. SPI clock frequencies of W25Q128JV of up to 133MHz are supported allowing equivalent clock rates of 266MHz (133MHz x 2) for Dual I/O and 532MHz (133MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. Additionally, the device supports JEDEC standard manufacturer and device ID and SFDP, and a 64-bit Unique Serial Number and three 256-bytes Security Registers.

W25Q128JVSIQ参数

FEATURES

 New Family of SpiFlash Memories

– W25Q128JV: 128M-bit / 16M-byte

– Standard SPI: CLK, /CS, DI, DO

– Dual SPI: CLK, /CS, IO0, IO1

– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3

– Software & Hardware Reset(1)Highest Performance Serial Flash

– 133MHz Single, Dual/Quad SPI clocks

– 266/532MHz equivalent Dual/Quad SPI

– 66MB/S continuous data transfer rate

– Min. 100K Program-Erase cycles per sector

– More than 20-year data retentionEfficient “Continuous Read”

– Continuous Read with 8/16/32/64-Byte Wrap

– As few as 8 clocks to address memory

– Allows true XIP (execute in place) operation Low Power, Wide Temperature Range

– Single 2.7 to 3.6V supply

– <1µA Power-down (typ.)

– -40°C to +85°C operating range

– -40°C to +105°C operating range

 Flexible Architecture with 4KB sectors

– Uniform Sector/Block Erase (4K/32K/64K-Byte)

– Program 1 to 256 byte per programmable page

– Erase/Program Suspend & Resume Advanced Security Features

– Software and Hardware Write-Protect

– Power Supply Lock-Down

– Special OTP protection

– Top/Bottom, Complement array protection

– Individual Block/Sector array protection

– 64-Bit Unique ID for each device

– Discoverable Parameters (SFDP) Register

– 3X256-Bytes Security Registers with OTP locks

– Volatile & Non-volatile Status Register Bits Space Efficient Packaging

– 8-pin SOIC 208-mil

– 16-pin SOIC 300-mil (additional /RESET pin)

– 8-pad WSON 6x5-mm / 8x6-mm

– 24-ball TFBGA 8x6-mm (6x4/5x5 ball array)

– 24-ball WLCSP

– Contact Winbond for KGD and other options

Note: 1. Hardware /RESET pin is only available on

TFBGA or SOIC16 packages

W25Q128JVSIQ封装设计图

W25Q128JVSIQ型号解析