SST39VF3201
Features:
Organized as 2M x16: SST39VF3201/3202
Low Power Consumption (typical values at 5 MHz)– Active Current: 9 mA (typical)– Standby Current: 3 µA (typical)– Auto Low Power Mode: 3 µA (typical)
Hardware Block-Protection/WP# Input Pin– Top Block-Protection (top 32 KWord)for SST39VF3202– Bottom Block-Protection (bottom 32 KWord)for SST39VF3201
Sector-Erase Capability– Uniform 2 KWord sectors
Block-Erase Capability– Uniform 32 KWord blocks
Chip-Erase Capability
Summary
*Not Recommended For New Design*
The SST39VF3201 device is organized in 2M x16, The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF3201 writes (Program or Erase) with a 2.7-3.6V power supply. This device conforms to JEDEC standard pinouts for x16 memories.
Additional Features
Organized as 2M x16: SST39VF3201/3202
Low Power Consumption (typical values at 5 MHz)– Active Current: 9 mA (typical)– Standby Current: 3 µA (typical)– Auto Low Power Mode: 3 µA (typical)
Hardware Block-Protection/WP# Input Pin– Top Block-Protection (top 32 KWord)for SST39VF3202– Bottom Block-Protection (bottom 32 KWord)for SST39VF3201
Sector-Erase Capability– Uniform 2 KWord sectors
Block-Erase Capability– Uniform 32 KWord blocks
Chip-Erase Capability
Erase-Suspend/Erase-Resume Capabilities
Hardware Reset Pin (RST#)
Security-ID Feature– SST: 128 bits; User: 128 bits
Fast Erase and Word-Program:– Sector-Erase Time: 18 ms (typical)– Block-Erase Time: 18 ms (typical)– Chip-Erase Time: 40 ms (typical)– Word-Program Time: 7 µs (typical)
Packages Available– 48-lead TSOP (12mm x 20mm)– 48-ball TFBGA (6mm x 8mm)
All non-Pb (lead-free) devices are RoHS compliant
Parametrics
Temp Range (°C)
-40°C to +85°C
SST39VF3201
Features:
Organized as 2M x16: SST39VF3201/3202
Low Power Consumption (typical values at 5 MHz)– Active Current: 9 mA (typical)– Standby Current: 3 µA (typical)– Auto Low Power Mode: 3 µA (typical)
Hardware Block-Protection/WP# Input Pin– Top Block-Protection (top 32 KWord)for SST39VF3202– Bottom Block-Protection (bottom 32 KWord)for SST39VF3201
Sector-Erase Capability– Uniform 2 KWord sectors
Block-Erase Capability– Uniform 32 KWord blocks
Chip-Erase Capability
Summary
*Not Recommended For New Design*
The SST39VF3201 device is organized in 2M x16, The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF3201 writes (Program or Erase) with a 2.7-3.6V power supply. This device conforms to JEDEC standard pinouts for x16 memories.
Additional Features
Organized as 2M x16: SST39VF3201/3202
Low Power Consumption (typical values at 5 MHz)– Active Current: 9 mA (typical)– Standby Current: 3 µA (typical)– Auto Low Power Mode: 3 µA (typical)
Hardware Block-Protection/WP# Input Pin– Top Block-Protection (top 32 KWord)for SST39VF3202– Bottom Block-Protection (bottom 32 KWord)for SST39VF3201
Sector-Erase Capability– Uniform 2 KWord sectors
Block-Erase Capability– Uniform 32 KWord blocks
Chip-Erase Capability
Erase-Suspend/Erase-Resume Capabilities
Hardware Reset Pin (RST#)
Security-ID Feature– SST: 128 bits; User: 128 bits
Fast Erase and Word-Program:– Sector-Erase Time: 18 ms (typical)– Block-Erase Time: 18 ms (typical)– Chip-Erase Time: 40 ms (typical)– Word-Program Time: 7 µs (typical)
Packages Available– 48-lead TSOP (12mm x 20mm)– 48-ball TFBGA (6mm x 8mm)
All non-Pb (lead-free) devices are RoHS compliant
Parametrics
Op. Volt Range (V)
2.7 to 3.6
Temp Range (°C)
-40°C to +85°C